1. Field of the Invention
The present invention relates to a semiconductor integrated device and a manufacturing method for the same.
2. Description of Related Art
FIG. 22 shows a schematic view of a cross-section of a related-art typical semiconductor integrated device 1. As shown in FIG. 22, the semiconductor integrated device 1 has wells for PMOS transistors and NMOS transistors formed on a substrate 2. Each well has a tap 3 or 4 formed in its top. Lines 5, 6 via which to supply a power supply voltage VDD and ground voltage GND are connected to the taps 3, 4. By this means, ground voltage GND or power supply voltage VDD is supplied as a well potential to each well.
Technology for reducing semiconductor integrated devices in size is disclosed in Japanese Unexamined Patent Application Publication No. 2007-5763. In this Japanese Unexamined Patent Application Publication, an N-type buried layer is positioned in a P-type semiconductor substrate, and P-type and N-type wells are formed immediately under the surface of the P-type semiconductor substrate. The N-type well is electrically connected to the N-type buried layer. A P-type contact region is selectively formed through the N-type buried layer directly under the P-type well so that the P-type well is not electrically cut off the P-type semiconductor substrate by the N-type buried layer, and thereby the P-type well is electrically connected to the P-type semiconductor substrate.
With the above configuration, the N-type well is supplied with potential from the N-type buried layer, and the P-type well is supplied with potential via the P-type semiconductor substrate. Hence, a tap to supply potential to the P-type well does not need to be formed in the semiconductor substrate surface, and thus reduction in size of the semiconductor device and the like are possible.